1. Field of the Invention
The present invention relates to an address translation unit which supports a variety of page sizes.
2. Description of the Related Art
In managing partitioning of a segment into page sizes in a memory management unit (MMU), the address translation unit generates a 20-bit physical address in order to support a 4K page size because of using upper 20 bits of a 32-bit linear address for partitioning the page; a 12-bit physical address is generated in order to support a 1M page size because of using upper 12 bits of the 32-bit linear address for partitioning the page; a 11-bit physical address is generated in order to support a 2M page size because of using upper 11 bits of the 32-bit linear address for partitioning the page; and a 10-bit physical address is generated in order to support a 4M page size because of using upper 10 bits of the 32-bit linear address for partitioning the page.
FIG. 1 is a block diagram illustrating a conventional address translation unit supporting the variety of page sizes in the MMU. As shown in FIG. 1, the conventional micro-processor has a plurality of translation look aside buffer (TLB) 12, 13, 14 and 15 for supporting the page sizes of 4K, 1M, 2M, and 4M bytes respectively.
And, a page unit controller 11 provides the corresponding TLB with the corresponding linear address of the 32-bit linear address in response to the page sizes, and applies a 2-bit page size select signal to a physical address selector 16.
The physical address selector 16 selects one of the respective physical addresses outputted from each TLB in response to the page size select signal applied from the page unit controller 11 and outputs the selected physical address.
As described above, in the conventional address translation unit, routing and gate loads are bigger because the 32-bit linear address which was generated at the MMU is inputted to every TLB, and the conventional address translation unit needs the physical address selector in order to select one of the respective physical addresses which are outputted from each TLB. Therefore, the conventional address translation unit is difficult to the address translation of high speed and needs much area in order to realize TLBs.